DIGILENT Basys2 Simple Seven Segment Timer project using Verilog

Hello everyone, This a simple timer i designed using the DIGILENT-Basys2. This module start counting the time at the point of reset and keeps on counting.  I used Xilinx ISE design suite 14.5 for generating the bit file. Here is my verilog code and .ucf file.

Verilog Code

module clock1(
input reset,clock,
output [7:0] ss,
output [3:0] anode
    );
   
//timing
reg [25:0] counter;
reg [7:0] temps;
reg [3:0] an;
reg [3:0] d0;
reg [3:0] d1;
reg [3:0] d2;
reg [3:0] d3;
reg [3:0] num;
initial d0=4'b0000;
initial d1=4'b0000;
initial d2=4'b0000;
initial d3=4'b0000;

always@(posedge clock or posedge reset)
begin
   
    if(reset)
    counter<=0;
    else if(counter==50000000) begin
        counter<=0;
        if(d0==9) begin
            d0<=0;
            if(d1==5) begin
                d1<=0;
                if(d2==9) begin d2<=0;
                    if(d3==9) begin d3<=0;d2<=0;d1<=0;d0<=0;end
                    else d3<=d3+1;
                end
                else d2<=d2+1;
                end
            else d1<=d1+1;
           
        end
        else d0<=d0+1;
       
       
    end
    else
    counter<=counter+1;
end

reg [18:0] sync;

always@(posedge clock or posedge reset)
begin
    if(reset)
    sync<=0;
    else
    sync<=sync+1;

   
end

always@(*)
begin
    if(sync[18:17]==2'b00) begin
    an<=4'b1110;num<=d3; end
    else if(sync[18:17]==2'b01) begin
    an<=4'b1101;num<=d2; end
    else if(sync[18:17]==2'b10) begin
    an<=4'b1011;num<=d1; end
    else begin
    an<=4'b0111;num<=d0; end
end


always@(*)
begin
case(num)
4'b0000 : temps=~(8'b00111111);
4'b0001 : temps=~(8'b00000110);
4'b0010 : temps=~(8'b01011011);
4'b0011 : temps=~(8'b01001111);
4'b0100 : temps=~(8'b01100110);
4'b0101 : temps=~(8'b01101101);
4'b0110 : temps=~(8'b01111101);
4'b0111 : temps=~(8'b00000111);
4'b1000 : temps=~(8'b01111111);
4'b1001 : temps=~(8'b01100111);
4'b1010 : temps=~(8'b01110111);
4'b1011 : temps=~(8'b01111100);
4'b1100 : temps=~(8'b00111001);
4'b1101 : temps=~(8'b01011110);
4'b1110 : temps=~(8'b01111001);
4'b1111 : temps=~(8'b01110001);
endcase
end


assign ss=temps;
assign anode=an;

endmodule

.ucf File 

NET "anode[0]" LOC = K14;
NET "anode[1]" LOC = M13;
NET "anode[2]" LOC = J12;
NET "anode[3]" LOC = F12;
NET "ss[0]" LOC = L14;
NET "ss[1]" LOC = H12;
NET "ss[2]" LOC = N14;
NET "ss[3]" LOC = N11;
NET "ss[4]" LOC = P12;
NET "ss[5]" LOC = L13;
NET "ss[6]" LOC = M12;
NET "ss[7]" LOC = N13;

NET "clock" LOC = B8;
NET "reset" LOC = A7;